Some integrated circuit (IC) chips nowadays include embedded or on-chip memory (e.g., SRAM) inside the processing unit due to the increased demand of processing speed and memory space. For example, a processing unit that has machine learning capabilities may need to embed a cellular neural network (CNN) that includes multiple layers and hundreds or thousands of cells. This requires the processing unit to have embedded memory large and fast enough to handle frequent reading and/or writing of data associated with machine learning computations. It is also desirable to embed in the processing unit memory of high density, long endurance and fast access speed with lower power consumption.
STT memory, such as STT-MRAM, is an enabling non-volatile memory solution for achieving fast access (read/write) speed and small cell size with lower power consumption. However, embedding an STT memory inside a processing unit faces some challenges. For example, one way to make the embedded memory inside the processing unit is to build the memory on top of the last metal substrate of the logic circuit of the processing unit. Yet, the high stress from the making of multi-metal layers of the processing unit at a high temperature (usually at 400° C.) may cause wafer warpage and/or significant topography, which may result in memory yield loss and device performance degradation.
Another challenge in the making of embedded STT-RAM (such as STT-MRAM with magnetic tunnel junction (MTJ)) is the adjustable thermal treatment that is required to match MTJ materials for better performance. For example, for perpendicular magnetic anisotropy (PMA) STT, the free layer of MTJ may preferably use a film of lower B composition of CoxFeyBz. Films with lower B can result in structure matching to MgO during post-low temperature annealing. This structure matching is important for better PMA interface (for higher device thermal stability) and faster memory read (higher MR) for better reading. Typically, a post-annealing at a temperature of about 300 to 360° C. is required for low B films for 1 to 2 hours. However, the making of an embedded IC process will be at about 400° C., which requires high B composition due to B diffuse out. This results in lower MR and low device thermal stability.
Another challenge in the making of embedded STT-RAM is the surface roughness during the film growth or other fabrication processes and a need for controlling the surface smoothness. In making an embedded memory, a smooth surface before MTJ deposit is very critical for film growth and film properties. MTJ film to dielectric film adhesion is also important in preventing peeling during IC manufacturing processes.